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This gets rid of some more absolute addrs in the MIPS dynarec.
Tested on several platforms, we should be good.
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Will move also OAM structures to gain a few cycles per load/store.
Loads can also be optimized for an extra instruction per access.
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Also fix a regression on VITA.
Use gcc/OS cache flushing routines for MIPS32 instead of synci
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Make it better and more generic. Add support for MIPS32 and fix the
messy PSP code.
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This removes libco and all the usages of it (+pthreads).
Rewired all dynarecs and interpreter to return after every frame so that
libretro can process events. This required to make dynarec re-entrant.
Dynarecs were updated to check for new frame on every update (IRQ, cycle
exhaustion, I/O write, etc). The performance impact of doing so should
be minimal (and definitely outweight the libco gains). While at it,
fixed small issues to get a bit more perf: arm dynarec was not idling
correctly, mips was using stack when not needed, etc.
Tested on PSP (mips), OGA (armv7), Linux (x86 and interpreter). Not
tested on Android though.
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Affects at least SM Adv 4 on PSP, which doesn't load at all.
I think the MIPS pipeline does not like invalidating the Icache and
using it immediately after (seems to read an old value sometimes?).
Rewired it to not do that and instead jump to the handler directly.
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Fix some small issues, mainly associated with undefined behaviour
expressions
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