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2021-07-03Merge remote-tracking branch 'libretro/master' into pico-feneonloop
2021-07-01Add palette conversion routine for non-R2 MIPSDavid Guillen Fandos
Gated MIPS_HAS_R2_INSTS not used at the moment. Tested with qemu.
2021-06-22Fix the no-caller-saves bug for MIPSDavid Guillen Fandos
Seems that ABI mandates that we allocate space for arg0..4 even if we do pass them as registers. For some reason write_io_register<> functions write in that stack area (1 word) corrupting the s0 saved register. This seems to be a new gcc behaviour?
2021-06-21Add support for mips64n32David Guillen Fandos
This only needs some support to save/load state with 64 bit registers. Since pointers remain 32 bit, no extra changes are needed in the dynarec. Verified with qemu (qemu-mipsn32el) and miniretro.
2021-06-18Add preliminary support for non mips32r2 devicesDavid Guillen Fandos
This is required in PS2 but could also make older dingux devices run gpsp on retroarch
2021-06-16Rework patch handlers (MIPS)David Guillen Fandos
2021-06-16Minor cleanup in MIPS codeDavid Guillen Fandos
2021-05-20Minor mips asm cleanup and fixesDavid Guillen Fandos
2021-05-07Small optimization (~2-4%) and whitespace cleanup!David Guillen Fandos
Cleans up a ton of whitespace in cpu.c (like 100KB!) and improves readability of some massive decode statements. Added an optimization for PC-relative loads (pool load) in ROM (since it's read only and cannot possibily change) that directly emits an immediate load. This is way faster, specially in MIPS/x86, ARM can be even faster if we rewrite the immediate load macros to also use a pool.
2021-05-05Fix small buf and add cheat error messagesDavid Guillen Fandos
Some minor formating too
2021-05-05Adding Code Breaker cheat supportDavid Guillen Fandos
This works on both interpreter and dynarec. Tested in MIPS, ARM and x86, still needs some more testing, some edge cases can be buggy.
2021-05-05Merge remote-tracking branch 'libretro/master' into pico-feneonloop
2021-05-05Revert "Remove BIOS reserved translation area"neonloop
This reverts commit fb7ca09b019248b9a0aba481ea55386f71053d73. It seems that commit broke rolling in Minish Cap when using the ARM dynarec.
2021-04-26Fix RTC support for MIPSDavid Guillen Fandos
2021-04-04Fix palette writes in MIPSDavid Guillen Fandos
Was not writing to the right address (but decoded memory was working). Most game worked well except those that depend on modifying the existing palette bits (instead of copying from ROM/RAM). Fixes several games.
2021-04-03Do not use stack in mips stubsDavid Guillen Fandos
No need for it (faster) and avoid mis-aligning it across calls
2021-04-03Add instruction tracing, for testing purposesDavid Guillen Fandos
2021-03-26Move OAM RAM to stubs alsoDavid Guillen Fandos
Makes accesses more efficient for MIPS. Make accesses also fast for palette reads.
2021-03-26Move OAM update flag to a registerDavid Guillen Fandos
Fix a small bug in MIPS dynarec that affects non -G0 targets
2021-03-23Move caches to stub files to get around gcc 10David Guillen Fandos
Seems that using the __atribute__ magic for sections is not the best way of doing this, since it injects some default atributtes that collide with the user defined ones. Using assembly is far easier in this case. Reworked definitions a bit to make it easier to import from assembly. Also wrapped stuff around macros for easy and less verbose implementation of the symbol prefix issue.
2021-03-23Make ewram memory linealDavid Guillen Fandos
This saves a few cycles in MIPS and simplifies a bit the core. Removed the write map, only affects interpreter performance very minimally. Rewired ARM and x86 handlers to support direct access to I/EWRAM (and VRAM on ARM) to compensate. Overall performance is slightly better but code is cleaner and allows for further improvements in the dynarecs.
2021-03-16Simplify open load handling for MIPS and fix other archesDavid Guillen Fandos
Also rewrite a bit memory handlers for smaller functions.
2021-03-16Add Dingux supportDavid Guillen Fandos
Uses a different cache primitive and a differend madd(u) encoding. Also added a flag for BGR vs RGB color output (since PSP is assuming to be BGR for speed). Aside from that the ABI required some special function calls for PIC.
2021-03-16Remove old handlers from mips/stubDavid Guillen Fandos
2021-03-16Rewrite of the MIPS dynarec stubsDavid Guillen Fandos
This allows us to emit the handlers directly in a more efficient manner. At the same time it allows for an easy fix to emit PIC code, which is necessary for libretro. This also enables more platform specific optimizations and variations, perhaps even run-time multiplatform support.
2021-03-16Move a few more registers to contextDavid Guillen Fandos
This gets rid of some more absolute addrs in the MIPS dynarec. Tested on several platforms, we should be good.
2021-03-15Move palettes around to simplify MIPS dynarecDavid Guillen Fandos
Will move also OAM structures to gain a few cycles per load/store. Loads can also be optimized for an extra instruction per access.
2021-03-12Fix typoDavid Guillen Fandos
2021-03-12Improve and simplify dynarec JIT area.David Guillen Fandos
Also fix a regression on VITA. Use gcc/OS cache flushing routines for MIPS32 instead of synci
2021-03-12Improve cache flush magicDavid Guillen Fandos
Make it better and more generic. Add support for MIPS32 and fix the messy PSP code.
2021-03-08Remove libcoDavid Guillen Fandos
This removes libco and all the usages of it (+pthreads). Rewired all dynarecs and interpreter to return after every frame so that libretro can process events. This required to make dynarec re-entrant. Dynarecs were updated to check for new frame on every update (IRQ, cycle exhaustion, I/O write, etc). The performance impact of doing so should be minimal (and definitely outweight the libco gains). While at it, fixed small issues to get a bit more perf: arm dynarec was not idling correctly, mips was using stack when not needed, etc. Tested on PSP (mips), OGA (armv7), Linux (x86 and interpreter). Not tested on Android though.
2021-03-08Fix a ghost bug with some gamesDavid Guillen Fandos
Affects at least SM Adv 4 on PSP, which doesn't load at all. I think the MIPS pipeline does not like invalidating the Icache and using it immediately after (seems to read an old value sometimes?). Rewired it to not do that and instead jump to the handler directly.
2021-02-26Remove more dead codeDavid Guillen Fandos
2021-02-15More cleanups (mostly whitespace and unused stuff)David Guillen Fandos
2021-02-12Minor cleanup in ARM and MIPSDavid Guillen Fandos
Fix some small issues, mainly associated with undefined behaviour expressions
2019-10-20Get dynarec working again for PSPbmaupin
2014-12-11Reimplement cache invalidation codetwinaphex
2014-12-10cleanupsaliaspider
2014-12-10add a HAVE_MMAP check, cleanups.aliaspider
2014-12-10Add macro parameter 'opcode' to some macrostwinaphex
2009-05-21original source from gpsp09-2xb_src.tar.bz2notaz