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| author | Nebuleon Fumika | 2012-12-18 22:53:49 -0500 |
|---|---|---|
| committer | Nebuleon Fumika | 2012-12-18 22:53:49 -0500 |
| commit | e708c127fa51beab567a9ce0e3ab53b58c997773 (patch) | |
| tree | 647a8d7aa072ed1cb46ecfe800d4db85a155780d /source/changes.txt | |
| parent | 286bfd58050a13e2e0e30bb35a7a1d189ec7edd1 (diff) | |
| download | snes9x2005-e708c127fa51beab567a9ce0e3ab53b58c997773.tar.gz snes9x2005-e708c127fa51beab567a9ce0e3ab53b58c997773.tar.bz2 snes9x2005-e708c127fa51beab567a9ce0e3ab53b58c997773.zip | |
Un-inline a bunch of stuff.
With the MIPS instruction cache, this means that two consecutive SNES CPU instructions using e.g. the same addressing style or the same opcode have a chance that the second one will use the first one's code and that it will be cached.
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