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This saves a few cycles in MIPS and simplifies a bit the core.
Removed the write map, only affects interpreter performance very
minimally. Rewired ARM and x86 handlers to support direct access to
I/EWRAM (and VRAM on ARM) to compensate. Overall performance is slightly
better but code is cleaner and allows for further improvements in the
dynarecs.
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This is not really necessary since it can share area with ROM.
Performance impact should be very minimal (haven't noticed it myself)
and could be compensated (even by a positive offset) if we bump the ROM
cache area size.
Tested with several dynarecs.
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Also rewrite a bit memory handlers for smaller functions.
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This gets rid of some more absolute addrs in the MIPS dynarec.
Tested on several platforms, we should be good.
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Will move also OAM structures to gain a few cycles per load/store.
Loads can also be optimized for an extra instruction per access.
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This removes libco and all the usages of it (+pthreads).
Rewired all dynarecs and interpreter to return after every frame so that
libretro can process events. This required to make dynarec re-entrant.
Dynarecs were updated to check for new frame on every update (IRQ, cycle
exhaustion, I/O write, etc). The performance impact of doing so should
be minimal (and definitely outweight the libco gains). While at it,
fixed small issues to get a bit more perf: arm dynarec was not idling
correctly, mips was using stack when not needed, etc.
Tested on PSP (mips), OGA (armv7), Linux (x86 and interpreter). Not
tested on Android though.
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Fix a C func call while at it. This is a prerequisite to make the
dynarec re-entrant and get rid of libco
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Turns out this was not even used! No need to fix it then!
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This gets rid of stack usage (except for callback invocations) in the
dynarec execution code. A requirement to make the dynarec re-entrant.
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Fix some small issues, mainly associated with undefined behaviour
expressions
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I think this does not make a difference at all in the code, since PC is
treated in a special way anyway (reloaded with an immediate when read
and treated as an indirect branch when written). However for the sake of
completeness I'm undoing what I did. (The comma fix stays :P)
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Turns out there were a couple of very interesting and hard to track
bugs. A missing comma made the reg list too short, leaving the 31th
element at the mercy of the linker ordering algorithm, which seems to
work in some cases depending on the compiler version.
Also the cache flush code seemed not to work on my machine (OGA),
not sure why it wored in the past :/
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Not available on iOS/Android, only probably there on OpenPandora.
On top of that iOS 8+ deprecated the system() call, so would
probably be becoming obsolete on that platform.
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..to reduce dcache trashing
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newer gcc wants this
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it's causing a fault on Linux
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