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2021-08-01Revert "Add ROM mirroring and fix mult. cycle count"HEADpico-feneonloop
This reverts commit aafde6de7b2a28c1684c0e9fa62fee9a2a5398dd. This was causing trimmed roms to fail to load.
2021-07-03Restores extract/extend functions for old ARM devicesneonloop
2021-07-03Merge remote-tracking branch 'libretro/master' into pico-feneonloop
2021-05-19Minor optimizationDavid Guillen Fandos
2021-05-17Add ROM mirroring and fix mult. cycle countDavid Guillen Fandos
This should correct some minor issues in some games.
2021-05-17Fix ARM dynarec unaligned 32 bit loadsDavid Guillen Fandos
This might make a handful games slightly slower (but on the upper side they work now instead of crashing or restarting). Also while at it, fix some minor stuff in arm stubs for speed.
2021-05-07Small optimization (~2-4%) and whitespace cleanup!David Guillen Fandos
Cleans up a ton of whitespace in cpu.c (like 100KB!) and improves readability of some massive decode statements. Added an optimization for PC-relative loads (pool load) in ROM (since it's read only and cannot possibily change) that directly emits an immediate load. This is way faster, specially in MIPS/x86, ARM can be even faster if we rewrite the immediate load macros to also use a pool.
2021-05-05Fix small buf and add cheat error messagesDavid Guillen Fandos
Some minor formating too
2021-05-05Adding Code Breaker cheat supportDavid Guillen Fandos
This works on both interpreter and dynarec. Tested in MIPS, ARM and x86, still needs some more testing, some edge cases can be buggy.
2021-05-05Merge remote-tracking branch 'libretro/master' into pico-feneonloop
2021-05-05Revert "Remove BIOS reserved translation area"neonloop
This reverts commit fb7ca09b019248b9a0aba481ea55386f71053d73. It seems that commit broke rolling in Minish Cap when using the ARM dynarec.
2021-04-27Fix Vita port and likely some Linux/Android hidden issuesDavid Guillen Fandos
Using an invalid SP makes Vita crash (for an unkown reason) and makes things like C signal handlers crash (luckily Retroarch doesn't use them). It is also a violation of the ABI and not a great idea. Recycled some little used registers to free SP. Perf should be roughly the same.
2021-04-03Add instruction tracing, for testing purposesDavid Guillen Fandos
2021-04-02Add function decorators for easier debugging / profilingDavid Guillen Fandos
2021-03-30Improve indirect jumps in ARMDavid Guillen Fandos
Handle already translated blocks in the ARM asm to speed up indirect branches (affect some games more than others)
2021-03-30Improve ARM store handlersDavid Guillen Fandos
2021-03-26Fix 16 bit RAM stores (VRAM and OAM) in ARMDavid Guillen Fandos
2021-03-26Improve ARM store accessesDavid Guillen Fandos
2021-03-26Move OAM RAM to stubs alsoDavid Guillen Fandos
Makes accesses more efficient for MIPS. Make accesses also fast for palette reads.
2021-03-26Move OAM update flag to a registerDavid Guillen Fandos
Fix a small bug in MIPS dynarec that affects non -G0 targets
2021-03-23Move caches to stub files to get around gcc 10David Guillen Fandos
Seems that using the __atribute__ magic for sections is not the best way of doing this, since it injects some default atributtes that collide with the user defined ones. Using assembly is far easier in this case. Reworked definitions a bit to make it easier to import from assembly. Also wrapped stuff around macros for easy and less verbose implementation of the symbol prefix issue.
2021-03-23Make ewram memory linealDavid Guillen Fandos
This saves a few cycles in MIPS and simplifies a bit the core. Removed the write map, only affects interpreter performance very minimally. Rewired ARM and x86 handlers to support direct access to I/EWRAM (and VRAM on ARM) to compensate. Overall performance is slightly better but code is cleaner and allows for further improvements in the dynarecs.
2021-03-18asm fixes for clangDavid Guillen Fandos
2021-03-17Remove BIOS reserved translation areaDavid Guillen Fandos
This is not really necessary since it can share area with ROM. Performance impact should be very minimal (haven't noticed it myself) and could be compensated (even by a positive offset) if we bump the ROM cache area size. Tested with several dynarecs.
2021-03-16Simplify open load handling for MIPS and fix other archesDavid Guillen Fandos
Also rewrite a bit memory handlers for smaller functions.
2021-03-16Move a few more registers to contextDavid Guillen Fandos
This gets rid of some more absolute addrs in the MIPS dynarec. Tested on several platforms, we should be good.
2021-03-15Move palettes around to simplify MIPS dynarecDavid Guillen Fandos
Will move also OAM structures to gain a few cycles per load/store. Loads can also be optimized for an extra instruction per access.
2021-03-08Remove libcoDavid Guillen Fandos
This removes libco and all the usages of it (+pthreads). Rewired all dynarecs and interpreter to return after every frame so that libretro can process events. This required to make dynarec re-entrant. Dynarecs were updated to check for new frame on every update (IRQ, cycle exhaustion, I/O write, etc). The performance impact of doing so should be minimal (and definitely outweight the libco gains). While at it, fixed small issues to get a bit more perf: arm dynarec was not idling correctly, mips was using stack when not needed, etc. Tested on PSP (mips), OGA (armv7), Linux (x86 and interpreter). Not tested on Android though.
2021-03-05ARM dynarec: Do not use the stack at allDavid Guillen Fandos
Fix a C func call while at it. This is a prerequisite to make the dynarec re-entrant and get rid of libco
2021-03-05Remove dead codeDavid Guillen Fandos
Turns out this was not even used! No need to fix it then!
2021-03-04Minor improvements in ARM stubsDavid Guillen Fandos
This gets rid of stack usage (except for callback invocations) in the dynarec execution code. A requirement to make the dynarec re-entrant.
2021-02-12Minor cleanup in ARM and MIPSDavid Guillen Fandos
Fix some small issues, mainly associated with undefined behaviour expressions
2021-02-10Move r15 to reg_a0 (instead of reg_mem)David Guillen Fandos
I think this does not make a difference at all in the code, since PC is treated in a special way anyway (reloaded with an immediate when read and treated as an indirect branch when written). However for the sake of completeness I'm undoing what I did. (The comma fix stays :P)
2021-02-10Fix ARM dynarecDavid Guillen Fandos
Turns out there were a couple of very interesting and hard to track bugs. A missing comma made the reg list too short, leaving the 31th element at the mercy of the linker ordering algorithm, which seems to work in some cases depending on the compiler version. Also the cache flush code seemed not to work on my machine (OGA), not sure why it wored in the past :/
2020-10-08Add more forward declarationstwinaphex
2020-10-08Add forward declarationstwinaphex
2016-10-03(VITA) Dynarec workingFrancisco José García García
2016-08-14(VITA) Dynarec WIPFrancisco José García García
2016-08-08(VITA) Dynarec WIPFrancisco José García García
2015-07-30Add MSB_FIRST ifdefstwinaphex
2014-12-20Get rid of function_ccTwinaphex
2014-12-11arm/video_blend.S - add another __MACH__ hacktwinaphex
2014-12-11(ARM ASM) Add __MACH__ hack to get iOS port linking for nowtwinaphex
2014-12-11Reimplement cache invalidation codetwinaphex
2014-12-11Remove warm, keep only fallback cache invalidation routine.twinaphex
Not available on iOS/Android, only probably there on OpenPandora. On top of that iOS 8+ deprecated the system() call, so would probably be becoming obsolete on that platform.
2014-12-11(iOS) Compatibility patches pt. 1twinaphex
2014-12-11(ARM ASM) Use .globl instead of .globaltwinaphex
2014-12-10warm.h - change linux/ioctl.h include into sys/ioctl.h includetwinaphex
2014-12-10Code nits - get rid of '== NULL' / '!= NULL'twinaphex
2014-12-10cleanupsaliaspider