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Gated MIPS_HAS_R2_INSTS not used at the moment. Tested with qemu.
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Seems that ABI mandates that we allocate space for arg0..4 even if we do
pass them as registers. For some reason write_io_register<> functions
write in that stack area (1 word) corrupting the s0 saved register.
This seems to be a new gcc behaviour?
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This only needs some support to save/load state with 64 bit registers.
Since pointers remain 32 bit, no extra changes are needed in the
dynarec. Verified with qemu (qemu-mipsn32el) and miniretro.
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This is required in PS2 but could also make older dingux devices run
gpsp on retroarch
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Cleans up a ton of whitespace in cpu.c (like 100KB!) and improves
readability of some massive decode statements.
Added an optimization for PC-relative loads (pool load) in ROM (since
it's read only and cannot possibily change) that directly emits an
immediate load. This is way faster, specially in MIPS/x86, ARM can be
even faster if we rewrite the immediate load macros to also use a pool.
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Some minor formating too
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This works on both interpreter and dynarec.
Tested in MIPS, ARM and x86, still needs some more testing, some edge
cases can be buggy.
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This reverts commit fb7ca09b019248b9a0aba481ea55386f71053d73.
It seems that commit broke rolling in Minish Cap when using the ARM dynarec.
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Was not writing to the right address (but decoded memory was working).
Most game worked well except those that depend on modifying the existing
palette bits (instead of copying from ROM/RAM). Fixes several games.
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No need for it (faster) and avoid mis-aligning it across calls
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Makes accesses more efficient for MIPS. Make accesses also fast for palette
reads.
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Fix a small bug in MIPS dynarec that affects non -G0 targets
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Seems that using the __atribute__ magic for sections is not the best way
of doing this, since it injects some default atributtes that collide
with the user defined ones. Using assembly is far easier in this case.
Reworked definitions a bit to make it easier to import from assembly.
Also wrapped stuff around macros for easy and less verbose
implementation of the symbol prefix issue.
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This saves a few cycles in MIPS and simplifies a bit the core.
Removed the write map, only affects interpreter performance very
minimally. Rewired ARM and x86 handlers to support direct access to
I/EWRAM (and VRAM on ARM) to compensate. Overall performance is slightly
better but code is cleaner and allows for further improvements in the
dynarecs.
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Also rewrite a bit memory handlers for smaller functions.
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Uses a different cache primitive and a differend madd(u) encoding.
Also added a flag for BGR vs RGB color output (since PSP is assuming to
be BGR for speed).
Aside from that the ABI required some special function calls for PIC.
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This allows us to emit the handlers directly in a more efficient manner.
At the same time it allows for an easy fix to emit PIC code, which is
necessary for libretro. This also enables more platform specific
optimizations and variations, perhaps even run-time multiplatform
support.
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This gets rid of some more absolute addrs in the MIPS dynarec.
Tested on several platforms, we should be good.
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Will move also OAM structures to gain a few cycles per load/store.
Loads can also be optimized for an extra instruction per access.
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Also fix a regression on VITA.
Use gcc/OS cache flushing routines for MIPS32 instead of synci
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Make it better and more generic. Add support for MIPS32 and fix the
messy PSP code.
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This removes libco and all the usages of it (+pthreads).
Rewired all dynarecs and interpreter to return after every frame so that
libretro can process events. This required to make dynarec re-entrant.
Dynarecs were updated to check for new frame on every update (IRQ, cycle
exhaustion, I/O write, etc). The performance impact of doing so should
be minimal (and definitely outweight the libco gains). While at it,
fixed small issues to get a bit more perf: arm dynarec was not idling
correctly, mips was using stack when not needed, etc.
Tested on PSP (mips), OGA (armv7), Linux (x86 and interpreter). Not
tested on Android though.
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Affects at least SM Adv 4 on PSP, which doesn't load at all.
I think the MIPS pipeline does not like invalidating the Icache and
using it immediately after (seems to read an old value sometimes?).
Rewired it to not do that and instead jump to the handler directly.
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Fix some small issues, mainly associated with undefined behaviour
expressions
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